As international efforts to combat climate change and achieve carbon neutrality goals accelerate, nuclear technology is being proposed as a viable solution. In particular, unlike conventional large-scale nuclear power plants, Small Modular Reactors (SMRs) are attracting significant attention as a next-generation nuclear technology due to their versatile site applicability and flexible power supply capabilities. SMRs possess a more simplified structural design than conventional large reactors, utilizing system simplification and modularization to reduce process complexity, enhance safety, and secure economic advantages.

Based on the design experience of SMART, a previous SMR model, the Korea Atomic Energy Research Institute (KAERI) is participating in the development of innovative SMR technologies. Although the system configuration of an SMR is simplified compared to large-scale reactors, instrumentation technology capable of precisely monitoring operating conditions remains a critical factor in ensuring safety and control performance. Among these technologies, ex-core neutron flux monitoring observes reactor power variations in real-time by measuring the neutron flux leaking out of the reactor. The measured neutron flux data is generally utilized to perform essential functions for safety, startup, and control.

This study suggests a parallel processing framework for neutron and gamma pulse simulation. Given that individual pulses generate on a nanosecond scale, high-speed signal processing is strictly required for real-time simulation. Moreover, the exponential increase in pulse signals at higher reactor power levels necessitates parallel processing to accurately model the pulse pile-up phenomenon. Field-Programmable Gate Arrays (FPGAs) are employed to provide hardware-level parallelism, significantly enhancing computational efficiency. This paper proposes a single-pulse parallelization methodology, presents signal generation results across major operating ranges, and evaluates the hardware resource utilization of the parallel implementation.